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# 2514/U, 7th 'A' Main Road, Opp. to BBMP Swimming Pool, Hampinagar, Vijayanagar 2nd Stage. 560104 Bangalore IN
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# 2514/U, 7th 'A' Main Road, Opp. to BBMP Swimming Pool, Hampinagar, Vijayanagar 2nd Stage. Bangalore, IN
+918023404924 //d2pyicwmjx3wii.cloudfront.net/s/59c9e4669bd3e7c70c5f5e6c/ms.settings/5256837ccc4abf1d39000001/webp/59dafe26aef6e1d20402c4c3-480x480.png" [email protected]
6017c32337cd466297048529 74LS74 Dual JK Flip-Flop //d2pyicwmjx3wii.cloudfront.net/s/59c9e4669bd3e7c70c5f5e6c/60a78657bdb3c7403e436e3b/webp/ic-chips-ec.jpg

74LS74 - Dual JK Flip-Flop

Features
  • Two independent Negative Edge Triggered JK Flip-Flops
  • Standard Pin Arrangement
  • Fast Switching Times
  • Operating Temperature up to 70oC
  • Standard TTL Switching Voltages
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
 
*Image shown is a representation only.

 

 TT-ECK-4410
in stock INR 23.6
ELECTRON COMPONENT
1 1
ic-chips-ec-1000x1000.jpg

74LS74 Dual JK Flip-Flop

Sku: TT-ECK-4410
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₹23.6
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Sold By: tenettech
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Description of product

74LS74 - Dual JK Flip-Flop

Features
  • Two independent Negative Edge Triggered JK Flip-Flops
  • Standard Pin Arrangement
  • Fast Switching Times
  • Operating Temperature up to 70oC
  • Standard TTL Switching Voltages
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
 
*Image shown is a representation only.

 

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